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Tektronix Expands TLA 700 Series Logic Analyzers
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Tektronix Expands TLA 700 Series Logic Analyzers

Tektronix Expands TLA 700 Series Logic Analyzers

 

Tektronix Limited has announced TLA7PG2, a new pattern generator module, and the TLA7XM expansion mainframe for the TLA 700 Series Logic Analyzer family.

 

The TLA7PG2 is a multi-channel, programmable pattern generator module with sequential control that plugs into the TLA 700.  It generates necessary, but previously unavailable digital stimuli to simulate infrequently encountered test conditions in hardware design and software program testing. The TLA7PG2 stimulates the prototype with data from the simulator for extended analysis, and makes the powerful acquisition

technology of the TLA 700 Series accessible to design engineers who require an integrated pattern generation solution.

 

The company also introduced the TLA7XM expansion mainframe. This expansion chassis for the TLA 700 Series represents a breakthrough in the number of buses that can be monitored simultaneously. Combined with the TLA7PG2, designers now have a total of up to 1,024 stimulus channels or over 2,000 acquisition channels. Pattern Generation Enables Integrated Logic Analysis Solution.

 

Electronic design engineers, who design hardware for systems rely on the logic analyzer to test and evaluate subsystem performance and function early in the debug process. A pattern generator is necessary to stimulate electronic designs with ideal or faulty digital patterns for performing functional verification, debugging and stress testing.

 

The TLAPG2 is an ideal pattern generation solution in the design of systems where surrounding boards, ICs, or buses that normally provide data signals to the device under test are missing.  With the TLA7PG2, design engineers can place the circuit in a desired state, operate it at full speed, or single-step it through a series of states.

 

High- Performance Digital Stimulus Expands TLA 700 Family. The TLA7PG2 achieves greater versatility through larger channel count; higher data output rate and deeper pattern memory.  The TLA7PG2 features up to 64 channels per module and supports 268 MHz clock rate for data output. It achieves high performance with speeds of 268 million-vectors-per-second output and up to 2 Mb of memory.  The TLA7PG2 enables the testing of designs at speed through full performance up to the specified maximum clock rate.

 

The TLA7PG2 operates with a Windows user interface that communicates with the TLA 700 Series, and features the same look and feel of the flagship TLA Logic Analyzer family.

 

The company has also expanded the TLA7XM to mainframe. Paired with the TLA 700 Series logic analyzers, the TLA7XM will addresses the complex verification challenges associated with high-end microprocessor and embedded systems design.  Offering up to 2,176 logic analyzer channels which is more than twice the available capacity and up to 16 M of memory per channel, the combined products increase productivity by enabling design engineers to simultaneously monitor, debug and verify electronics systems containing multiple processors and buses.

 

The TLA 700 with expansion mainframe enables concurrent capture and correlation of real-time system faults to faster identify problem sources thus allowing engineers to maximize productivity and optimize system design. Product combination Supports Large Channel-count Applications Designed around the TLA 700 Series platform, the TLA7XM supports large channel-count applications found in high-end microprocessor and embedded systems design.

 

Addressing current and future system needs, the TLA7XM expands the TLA 700 Series to provide up to 16 total modules for a maximum of 2,176-logic analyzer, 64 digital storage oscilloscope, or 1024 pattern generator channels. With 16M of memory acquisition per channel, it allows for deep trace history across all channels-useful for correlating faults and quickly identifying problem areas.

 

Using the TLA7XM requires V3.1 of the TLA application software. In addition to supporting the TLA7XM, V3.1 provides new deep memory data management features such as sample suppression as well as new TLA connectivity capabilities. All current TLA 700 products can be easily upgraded to incorporate V3.1. TLA 700 Continues to Provide breakthrough Real-time Digital Systems Analysis The TLA 700 Series logic analyzers are a family of modular analysis tools that are used to acquire a wide range of real-time digital, analog and software data. The tools provide non-intrusive capabilities to monitor, capture and analyze system problems, including initialization failure, software crashes, and intermittent operation.  In the case of embedded systems, the TLA 700 Series can help designers capture and correlate real-time software and hardware operation to identify problems and maximize system performance.

 

Central to the TLA 700 Series is the MagniVu™ acquisition technology, a super-fast digital sampler that provides 500-picosecond timing resolution and 200- MHz state timing analysis on all channels, simultaneously, through a single probe. Pattern Generator Module Also Addresses Embedded Systems Design In a related announcement, Tektronix also announced today the TLA7PG2 pattern generator for the TLA 700 Series logic analyzer platform. This high-performance digital stimulus module enables functional verification, debugging and stress testing for embedded system hardware design. It generates necessary, which were previously unavailable digital stimuli to simulate infrequently encountered test conditions in hardware design and software program testing. The TLA7PG2 achieves greater versatility through larger channel count, higher data output rate and deeper pattern memory.

 

Combined with the new TLA7XM expansion mainframe, designers now have a total of up to 1,024 stimulus channels or over 2,000 acquisition channels. This powerful combination of stimulus and acquisition will enable embedded system design engineers to debug the most complex of digital applications with maximum flexibility and configurability.

 




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Last modified on 26 February 2000